In field effect transistors (hereinafter referred to as FETs), current flowing between source and drain electrodes is controlled by voltage applied to a gate electrode, that is, an input signal to the gate electrode is amplified and current equivalent to the signal amplified is output from the drain electrode. An FET in which electrons travel with high mobility through a two-dimensional electron gas layer is called a high electron mobility transistor (hereinafter referred to as HEMT), and the HEMT operates in a high frequency region of 40 GHz or more. Although the HEMT has a drawback in its low gate junction breakdown voltage, a HEMT with a recess structure achieves a gate junction breakdown voltage as high as that of a silicon device.
FIG. 71 is a sectional view illustrating a conventional HEMT employing an InP substrate. In the figure, reference numeral 1 designates an InP substrate. An InAlAs buffer layer 2, an InGaAs channel layer 3, an n type InAlAs electron supply layer 4, an InAlAs Schottky junction formation layer 5, and an n type InGaAs ohmic contact layer 7 are successively disposed on the InP substrate 1. A gate recess penetrates the n type InGaAs ohmic contact layer 7 and reaches into the InAlAs Schottky junction formation layer 5, and a gate electrode 8 is disposed in the recess. A source electrode 9 and a drain electrode 10 are disposed on the n type InGaAs ohmic contact layer 7 spaced from each other. In this HEMT, current flows through the InGaAs channel layer 3 between the source and drain electrodes. This current is hereinafter referred to as drain current.
FIG. 73 is a sectional view illustrating a conventional MISFET (Metal Insulator Semiconductor FET) employing an InP substrate. In the figure, reference numeral 1 designates an InP substrate. An InAlAs buffer layer 2, an n type InGaAs channel layer 13, an InAlAs Schottky junction formation layer 5, and an n type InGaAs ohmic contact layer 7 are successively disposed on the InP substrate 1. A gate recess penetrates the n type InGaAs ohmic contact layer 7 and reaches into the InAlAs Schottky junction formation layer 5, and a gate electrode 8 is disposed in the recess. A source electrode 9 and a drain electrode 10 are disposed on the n type InGaAs ohmic contact layer 7 spaced from each other. In this MISFET, drain current flows through the n type InGaAs channel layer 13.
FIG. 74 is a sectional view illustrating a conventional HEMT employing a GaAs substrate. In the figure, reference numeral 14 designates a GaAs substrate. A GaAs buffer layer 15, an n type AlGaAs electron supply layer 16, and an n type GaAs ohmic contact layer 17 are successively disposed on the GaAs substrate 14. A source electrode 9 and a drain electrode 10 are disposed on the n type GaAs ohmic contact layer 17 spaced from each other. In this HEMT, drain current flows through the GaAs buffer layer 15 in the vicinity of the boundary between the buffer layer 15 and the n type AlGaAs electron supply layer 16.
FIG. 75 is a sectional view illustrating a conventional MISFET employing a GaAs substrate. In the figure, reference numeral 14 designates a GaAs substrate. A GaAs buffer layer 15, an n type GaAs channel layer 18, an AlGaAs Schottky junction formation layer 19, and an n type GaAs ohmic contact layer 17 are successively disposed on the GaAs substrate 14. A gate recess penetrates the n type GaAs ohmic contact layer 17 and reaches into the AlGaAs Schottky junction formation layer 19, and a gate electrode 8 is disposed in the recess. A source electrode 9 and a drain electrode 10 are disposed on the n type GaAs ohmic contact layer 17 spaced from each other. In this MISFET, drain current flows through the n type GaAs channel layer 18.
FIG. 76 is a sectional view illustrating a conventional MESFET (Metal Semiconductor FET) employing a GaAs substrate. In the figure, reference numeral 14 designates a GaAs substrate. A GaAs buffer layer 15, an n type GaAs channel layer 18, and an n type GaAs ohmic contact layer 17 are successively disposed on the GaAs substrate 14. A gate recess penetrates the n type GaAs ohmic contact layer 17 and reaches into the n type GaAs channel layer 18, and a gate electrode 8 is disposed in the recess. A source electrode 9 and a drain electrode 10 are disposed on the n type GaAs ohmic contact layer 17 spaced from each other. In this MESFET, drain current flows through the n type GaAs channel layer 18.
FIGS. 72(a)-72(c) illustrate a method for producing the HEMT on the InP substrate shown in FIG. 71.
Initially, on the InP substrate 1, the InAlAs buffer layer 2, the InGaAs channel layer 3, the n type InAlAs electron supply layer 4, the InAlAs Schottky junction formation layer 5, and the n type InGaAs ohmic contact layer 7 are successively grown by a crystal growth method (FIG. 72(a)). Then, the source and drain electrodes 9 and 10 are formed on the n type InGaAs ohmic contact layer 7 using vapor deposition and lift-off (FIG. 72(b)). Then, photoresist is deposited on the whole surface and patterned to form a photoresist mask 50. Then, portions of the n type InGaAs ohmic contact layer 7 and the InAlAs Schottky junction formation layer 5 are etched away using the photoresist mask 50, forming the gate recess (FIG. 72(c)). Then, a gate metal is deposited on the surface and the photoresist mask 50 and the overlying portions of the gate metal are removed by lift-off to form the gate electrode 8, resulting in the HEMT of FIG. 71.
A description is given of a heterojunction bipolar transistor (hereinafter referred to as HBT). In the HBT, current flowing between collector and emitter layers is controlled by current flowing through a base layer, that is, amplification is achieved by controlling the current flowing through the emitter layer with a small current flowing through the base layer. When the energy band gap of the emitter layer is larger than that of the base layer, a large amplification factor is achieved.
FIG. 77 is a sectional view illustrating a prior art HBT employing an InP substrate. In the figure, reference numeral 1 designates an InP substrate. An n type InGaAs collector layer 100 having a ridge 100a is disposed on the InP substrate 1, and collector electrodes 105 are disposed on the collector layer 100 at opposite sides of the ridge 100a. A p type InGaAs base layer 101 having a ridge 101a is disposed on the ridge 100a of the collector layer 100, and base electrodes 106 are disposed on the base layer 101 at opposite sides of the ridge 101a. An n type InAlAs emitter layer 103 and an n.sup.+ type InGaAs emitter contact layer 104 are disposed on the ridge 101a of the base layer 101. An emitter electrode 107 is disposed on the n.sup.+ type InGaAs emitter contact layer 104.
A method for producing the HBT of FIG. 77 is illustrated in FIGS. 78(a)-78(c).
Initially, on the InP substrate 1, the n type InGaAs collector layer 100, the p type InGaAs base layer 101, the n type InAlAs emitter layer 103, and the n.sup.+ type InGaAs emitter contact layer 104 are successively grown by a crystal growth method (FIG. 78(a)). Then, a first photoresist layer 150 is formed on the n.sup.+ type InGaAs emitter contact layer 104 using conventional photolithography and, thereafter, the n.sup.+ type InGaAs emitter contact layer 104 and the n type InAlAs emitter layer 103 are etched using the photoresist layer 150 as a mask. Since the unmasked portions of the n type InAlAs emitter layer 103 have to be completely removed and excessive etching is carried out therefor, upper portions of the p type InGaAs base layer 101 are also etched away (FIG. 78(b)). After removing the first photoresist layer 150, a second photoresist layer 151 is formed over the emitter contact layer 104 extending on portions of the base layer 101 by conventional photolithography, and the p type InGaAs base layer 101 is etched using the second photoresist layer 151 as a mask. Since the unmasked portions of the base layer 101 have to be completely removed and excessive etching is carried out therefor, upper portions of the n type InGaAs collector layer 100 are also etched away (FIG. 78(c)). Thereafter, the collector electrodes 105, the base electrodes 106, and the emitter electrode 107 are formed by vapor deposition and lift-off, completing the HBT of FIG. 77.
In the above-described FETs, the length of the channel, through which current flows from the source to drain, Greatly influences electric characteristics of the FET, and the channel length is determined by the depth of the gate recess. Since the depth of the gate recess is usually calculated from the etching speed and the etching time, variations in the etching time directly cause variations in transistor characteristics.
Meanwhile, in the above-described HBT, when the n type emitter layer disposed on the p type base layer is etched to expose the surface of the base layer, the excessive etching is carried out considering the variations in the etching depth, so that the upper portion of the base layer is unfavorably etched away. Since the base layer is usually as thin as about 0.1 micron, even the slight etching of the upper portion of the base layer adversely affects the effective thickness of the base layer, resulting in variations in the electric characteristics of the HBT.